1. Field of the Invention
The invention relates to a thin film transistor, and more particularly to a thin film transistor (TFT) for a low temperature polysilicon (LTPS) display.
2. Description of the Related Art
As shown in FIG. 1, a conventional top gate type TFT comprises a substrate 100, a polysilicon layer 102 on the substrate 100, a gate insulating layer 104 on the polysilicon layer 102, a gate electrode 106 on the gate insulating layer 104, an dielectric interlayer 108 on the gate electrode 106, and source and drain electrodes 112a, 112b electrically connected to the source and drain regions 102b and 102c of the polysilicon layer 102 by means of the plugs 110a and 110b, respectively. The gate electrode 106 may include Mo or W. Stress is typically generated during deposition of films and thermal processes and remains in or between films, e.g. between the gate electrode and gate insulating layer. Stress is also generated by material defects.
FIG. 2 shows a Vg-Id curve representing the relationship of gate voltage vs. drain current for a conventional thin film transistor. Referring to FIG. 2, electric properties may degrade due to the existence of stresses between the metal gate electrode and gate insulating layer. The Vg-Id curve apparently shifts to the negative direction of X-axis (Vg) when voltages of about −15˜20V and 10V are respectively applied to the gate electrode and drain electrode.
As described above, it is well known that the existence of stress between the metal gate electrode and gate insulating layer may effect the stability of a thin film transistor. Accordingly, a thin film transistor with stable electrical properties and operation is desirable.